Verification Engineering Lead/Manager

· BS in EE with 3+ years of experience or MS in EE with 1+ year experience · Knowledge of at least one of high-speed interfaces like USB, MIPI, PCIe, Ethernet, DP, · Knowledge of two or three of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, SPI · Experience managing a verification team · Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti · Fluent in verification languages such as UVM/OVM/System Verilog, Vera, Verilog · Experience in writing Test-plans and creating directed and random test cases · Strong scripting skills in Perl, Python, Linux shells etc. · Strong problem-solving skill to quickly identify and provide solution under tight schedule pressure · Strong analytical problem solving and attention to details · Team player with interest in filing up gaps in product development as needed · Good written and verbal communication skills · Good technical documentation skills · Good interpersonal skills, self-motivated, self-starter