Senior Digital/RTL IC Design Engineer

BS/BE/MS/MTech + 5 years or equivalent experience in high-performance digital or mixed-signal IC development in advanced CMOS processes Strong foundation in digital design concepts for complex ASICs Hands on experience with the Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc Strong understanding of digital design for mixed signal control loops and designing Verilog code to control analog circuits (e.g. digital backend for ADC, digital PLL, etc) Familiarity with behavioral Verilog code, including wreals Ability to write thorough testbenches Preferred knowledge of Genus, Tempus, Modus and other Cadence tool set used for ASIC design flow Excellent understanding of SystemVerilog Knowledge of SystemVerilog assertions preferred Familiarity with place and route tool flow using Innovus preferred but not mandatory Basic understanding of digital signal processing – MATLAB understanding preferred Extensive experience with synthesis flow in nano-meter scale CMOS Extensive experience with place and route flow interface Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating Familiarity with timing closure and static timing analysis tools with the MMMC modes Experience with scan chain vector generation and verification Experience with flow automation through scripting – shell scripts, Makefile, Python or similar languages Familiarity with Cadence Encounter tool flow preferred but not mandatory