Senior SoC Digital Verification Engineer, Multimedia Lab

About the team

Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

Responsibilities

• Verification Planning: Deeply analyze architecture and design specifications to develop comprehensive and high-coverage module-level, subsystem-level, or SoC system-level Test Plans. - Environment Development: Build from scratch or maintain highly reusable and automated advanced verification environments (Testbench) and components (Scoreboard, Monitor, Sequence, etc.) based on UVM methodology. -Test Execution & Closure: Develop high-quality testcases, execute Constrained Random and Directed tests, and drive Functional and Code Coverage to 100% closure. -System-Level Verification: Responsible for Gate-Level Simulation (GLS) and SDF back-annotated timing simulation. Assist in FPGA prototyping and Hardware/Software co-debugging on Emulation platforms (e.g., Palladium/ZeBu). - Flow Optimization: Develop and maintain regression testing scripts and automation tools to continuously improve the team's overall verification efficiency and compute resource utilization.