Senior Principal Design Engineer

The candidate shall be responsible for:

1. SoC u-Architecture for Clocking, Reset, Core & Interconnects, Power Management, Debug & Trace, Functional Safety, Security, IP/Subsystems integration etc.
2. SoC RTL Integration using state-of-the-art tools, flows & methodologies
3. LINT/CDC/RDC signoffs for the highest design quality
4. Handoff checks including Verification smokesuite and express Synthesis
5. Continuous learning using 3X5 Why based Root cause analysis, DFMEA, Lessons Learned for the product family
6. Requirements management and traceability including IS026262 / CMMi and other compliance requirements, working closely with System Architects, Applications, Design & Verification teams, Product & Test engineering, PMO and support functions
7. Overseeing technical documentation in close collaboration with information development team
8. Conducting IP Integration reviews, BE reports reviews for concurrent engineering
9. Driving key SoC design methodologies in close collaboration with global cross functional functional teams, Design Enablement etc.
10. Mentoring other engineers based on deep core competence and expertise

Soft skills expected:

1. Excellent collaboration skills and team work
2. Excellent verbal & written communication skills
3. Excellent presentation skills
4. Passion and can-do attitude

More information about NXP in India...

#LI-9415