Principal Design Verification Engineer

About the Team The Digital Engineering group is a highly collaborative organization comprising experienced ASIC and Systems engineers with deep expertise across architecture, logic design, verification, physical design, hardware–software co‑simulation, FPGA prototyping, and firmware development. The team brings together decades of cumulative industry experience and operates at the forefront of modern semiconductor design. We leverage advanced semiconductor process technologies and industry‑standard, state‑of‑the‑art EDA tools to deliver high‑quality silicon solutions. Our scope spans the full SoC development lifecycle, from architectural definition through verification, validation, and final product delivery. Senior/Staff ASIC Verification Engineer (Typically, 10–12 years of industry experience) Responsibilities Lead verification efforts for complex IPs or sub‑systems, contributing to SoC‑level verification strategy under guidance from principal/architect‑level engineers. Design, develop, and maintain SystemVerilog/UVM‑based verification environments, including agents, scoreboards, monitors, checkers, assertions, and functional coverage. Contribute to verification planning, translating architectural specifications into detailed test plans and coverage models, and ensuring alignment with overall project verification goals. Develop UVM test sequences, including constrained‑random, directed, and layered sequences, and participate in defining stimulus strategies to achieve coverage closure. Drive verification closure for owned blocks, tracking functional, code, assertion, and power coverage, identifying gaps, and proposing corrective actions. Participate in low‑power verification flows, including UPF/CPF integration and validation of power states and transitions at block and sub‑system levels. Support HW–FW co‑verification activities, including development of C/C++ testcases for simulation, emulation, or FPGA prototyping, and assist with early firmware bring‑up. Debug complex RTL and gate‑level issues, working closely with design and architecture teams to root‑cause functional, timing, and power‑related problems. Contribute to regression infrastructure, including test triage, failure analysis, and improving regression efficiency and stability. Collaborate effectively with cross‑functional teams (design, firmware, validation, and architecture) to ensure timely and high‑quality delivery. Mentor junior verification engineers, providing technical guidance, code reviews, and best‑practice recommendations. Qualifications / Skills Strong track record of block or sub‑system verification ownership, with experience contributing to multiple successful tape‑outs. Advanced proficiency in SystemVerilog and UVM, with hands‑on experience building reusable and maintainable verification components. Solid understanding of ASIC verification methodologies, including: Verification planning and execution Directed and constrained‑random testing Functional, code, and assertion coverage Assertion‑based verification Low‑power verification using UPF/CPF Experience with C/C++‑based test development for HW–FW simulation, emulation, or prototyping environments. Working knowledge of scripting languages such as Python or Perl for automation, debug, and regression support. Familiarity with standard development and tracking tools, including Git, Jira, and Confluence. Strong analytical and debugging skills, with the ability to work independently on complex verification problems. Clear communication skills and a collaborative mindset, capable of influencing technical decisions within the immediate team. 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