Senior STA Engineer, Sub-chip

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing

• Perform advanced Static Timing Analysis (STA) for HSIO at chiplet and FC level.

• Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.

• Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.

• Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.

• AI use for timing optimization and data analysis.

What we need to see

• B.SC./ M.SC. in Electrical Engineering.

• At least 5+ years of hands-on STA experience.

• Experience in Prime Time and signoff methodologies.

• A great teammate who thrives in a collaborative environment.

• AI tools orientation or alternatively a desire to learn.

Ways to stand out from the crowd

• Agentic Frameworks.

• AI prompting experience.

• Experience in Linux environments.

• TCL, Python, shell scripting abilities.

• Experience with data collection and analysis.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!