Silicon Engineer

Contributes to the verification of components used in Fabric Interconnect. Learns about the design and interacts with partner teams to define verification strategies and test plans. Develops UVM-based or Formal verification environments and run and debug simulations to drive quality. Applies random-stimulus and coverage-based techniques to find bugs and meet test plan goals. Innovates to improve verification efficiency through methodologies or tools. Applies industry leading generative AI solutions to verification work. Coaches and mentors others in your areas of expertise. Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field OR equivalent experience. Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ years technical engineering experience OR equivalent experience. Exposure to Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols. Exposure to one or more of the following: fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges. Understanding of IP verification from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff. Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking. Aptitude for writing scripts/software with industry standard languages like Python. Experience applying generative AI to day-to-day tasks.