Senior Quantum Analog Layout Engineer

Deliver Schematic-to-Graphic Database System (GDS) layouts for cutting-edge, high-performance, high-speed, low-power IP designs, including interconnectivity solutions and foundational Analog circuit blocks. Execute these layouts across multiple process nodes, including deep Fin Field-Effect Transistor (FinFET), following industry best practices. Develop plans for Analog Mask Layout execution and follow processes and methodologies to deliver IP blocks. Coordinate tasks with junior layout team members as needed. Using Cadence Virtuoso (or other equivalent) design tools and flows; perform layout implementation of analog-intensive IPs and help establish flows, methodologies, and processes for execution alongside peers. Support the on-boarding and off-boarding of contingent layout staff and vendor partners as needed; help direct their day-to-day execution to ensure quality and schedule are met. Work with other members of the team to deliver IPs, including project planning, schedule tracking, and report generation. Follow, augment, or put in place processes and methodologies for high-quality execution alongside peers. Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment OR equivalent experience. Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation). Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through hardware development. 10+ years of experience in Analog Mask Layout execution and IP delivery, including delivery of medium-to-large complexity analog blocks into mass production. 5+ years of lead experience covering day-to-day task coordination and overall delivery responsibilities across a layout team. Proficient use of Electronic Design Automation (EDA) tools from Cadence, Mentor, and Synopsys, including advanced Schematic-Driven Layout (SDL). Hands-on layout experience with high-performance analog blocks such as Voltage-Controlled Oscillators (VCOs), charge pumps, interpolators, bandgap references, Operational Transconductance Amplifiers (OTAs), Phase-Locked Loops (PLLs), Analog-to-Digital and Digital-to-Analog Converters (ADCs/DACs), Low-Dropout Regulators (LDOs), Serializer/Deserializers (SerDes), and other foundational analog blocks. In-depth knowledge of analog design and layout guidelines for high-performance, high-speed, and/or low-power designs, including floor-planning, block-level routing, and large macro-level assemblies. Knowledge of industry-standard analog layout techniques such as common-centroid layout, matching, symmetrical layouts, signal shielding, use of dummy devices, and thermal-aware layouts with consideration for Electromigration/IR-drop (EM/IR) and other analog-specific guidelines. Demonstrated ability to coordinate execution with external vendors and contingent staff, including scoping deliverables, tracking progress, and accepting completed work. Ability to learn cryogenic Process Design Kits (PDKs) and apply analog layout techniques to designs that operate at cryogenic temperatures.