Principal Quantum Systems Architect

Define the system architecture for scalable quantum control and readout across room-temperature and cryogenic domains Drive architectural direction for heterogeneous compute platforms supporting control, measurement, and feedback workloads Establish system partitioning and co-design strategies across hardware, firmware, software, and quantum systems Define communication, synchronization, and dataflow architectures enabling deterministic, low-latency operation at scale Lead system-level trade-offs and guide platform evolution toward scalable, production-ready quantum systems Doctorate in Computer Science, Software Engineering, Mathematics, Physics, Physical Sciences, or related field AND 3+ years software industry experience, including research and/or development of commercial software, compilers, scientific computing applications, or multi-component systems OR Master's Degree in Computer Science, Software Engineering, Mathematics, Physics, Physical Sciences, or related field AND 4+ years software industry experience, including research and/or development of commercial software, compilers, scientific computing applications, or multi-component systems OR Bachelor's Degree in Computer Science, Software Engineering, Mathematics, Physics, Physical Sciences, or related field AND 6+ years software industry experience, including research and/or development of commercial software, compilers, scientific computing applications, or multi-component systems OR equivalent experience. 6+ years programming experience in related programming languages. 6+ years experience in a collaborative environment. Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through both hardware and software development. Proven experience designing complex compute or signal-processing architectures (e.g., SoCs, distributed systems, accelerators, networking fabrics) Proficient understanding of system architecture fundamentals (compute, memory, interconnects, data movement, HW/SW partitioning) Experience driving architectural trade-offs across performance, scalability, power, and reliability Demonstrated leadership in cross-functional hardware/software co-design initiatives Experience with RF signal processing, instrumentation, or measurement systems Familiarity with quantum control, readout, or error correction concepts Experience with FPGA, ASIC, or custom accelerator technologies Exposure to cryogenic or constrained computing environments Experience defining scalable architectures for emerging compute platforms Track record of architecturally guiding the delivery of large-scale systems from concept through production