Principal Quantum Design Verification Engineer

Your responsibilities will include defining pre-silicon Simulation plans and post-silicon Validation/Characterization plans for SoC and Intellectual Property (IP) blocks, and coordinating individuals, contingent staff, and external vendors to deliver a high-quality design. Own verification environments and tests for IP and SoC designs, and validate designs in simulation with both pre- and post-layout Register-Transfer Level (RTL) and netlists. Coordinate the execution of contingent staff and external vendors to ensure verification deliverables meet specification and schedule. Set up and manage databases and flows for SoC and IP repositories; set up bug-tracking systems and log, track, manage, and close bugs and issues; drive milestone reviews and status reports. Create test plans for pre-silicon simulation verification across both digital and analog components, including the development of Analog Mixed-Signal (AMS) simulation models. Collaborate with the Design For Test (DFT) team to test DFT features. Align verification methodologies with wider teams and drive continuous improvement to Design Verification processes for at-scale execution. Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams. Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment OR equivalent experience. Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation). Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through hardware development. 10+ years of design verification experience, including verification of complex SoC or large IP blocks delivered to production. 5+ years of experience coordinating verification across large SoC or IP programs, including establishing verification flows and methodology. Hands-on expertise with Universal Verification Methodology (UVM), Open Verification Methodology (OVM), and SystemVerilog. Experience building testbenches, generating stimulus, creating simulation environments, and debugging complex designs. Experience with Analog Mixed-Signal (AMS) verification across the design lifecycle, including analog and digital interface verification, AMS modeling and simulation, and silicon characterization through release to production. Proficiency in MATLAB for complex modeling and visualization. Proficiency in a scripting language such as Python, Ruby, or Perl, including automation of simulation and data analysis. Experience writing tests in C and C++. Background verifying complex chips such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), AI accelerators, or networking SoCs.