Fabric IP Designer

Be part of a design team developing advanced components of the memory sub-system Develop automation and AI based solutions to improve organizational efficiency Own design blocks within complex, coherent fabrics, and bridge IPs Be responsible for all aspects of the design flow including RTL coding, Lint, CDC, timing closure, etc Collaborate with team members to define interfaces and make optimal design choices Work with verification teams to develop test plans and ensure functional correctness Interface with performance modeling, physical design, design for test, and other teams to optimize tradeoffs Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience. This role will requires access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 3+ years of digital logic design experience for ASIC or FPGA. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting, etc). Demonstrated proficiency in Computer Architecture, Digital Design, CPU/SoC design principles as part of CPU, SoC and/or IP development Demonstrated experience and knowledge of design clock crossings and power/UPF. Ability to write scripts using Perl, Tcl, Python etc. Experience using generative AI technologies, agent/skill development Experience in building and integrating any of the IPs such as protocol bridges, PCIe, cache controllers, memory controllers and DDR, security engines. Experience in building functional fabrics using coherent and non-coherent protocols. Familiarity with Industry standard interface protocols such as AXI or CHI. Familiarity with synthesis and STA tools.