Design Verification Engineer

The candidate for this position will be expected and able to complete the following responsibilities: Own or lead verification of components used in Fabric Interconnect Learn about the design and interact with partner teams to define verification strategies and test plans Develop UVM-based or Formal verification environments and run and debug simulations to drive quality Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals Innovate to improve verification efficiency through methodologies or tools Apply industry leading generative AI solutions to verification work Coach and mentor others in your areas of expertise Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 1+ years of pre-silicon subsystem or IP verification experience. Demonstrated experience inverification of designs that utilize Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols Demonstrated understanding in one or more of the following: fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges Experience with writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking Aptitude for writing scripts/software with industry standard languages like Python Experience applying generative AI to day-to-day tasks