Staff Engineer, Design For Test

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Staff Engineer, Design For Test at Marvell, you will be an integral DFT execution contributor within the Custom Silicon Engineering team. You will apply your DFT knowledge to implement, verify, and validate DFT structures on advanced ASIC/SoC designs while developing your skills in DFT methodology, automation, and architecture. This role offers significant learning and growth opportunity in a team working on industry-leading custom AI, XPU, and high-performance compute silicon programs. What You Can Expect Execute DFT insertion flows for assigned IP blocks or SoC partitions on Custom and XPU programs using Siemens Tessent or Synopsys TestMax, including scan, MBIST, and IJTAG insertion. Run ATPG pattern generation and simulation (SAF/TDF) for assigned design blocks; validate coverage closure and resolve pattern generation failures. Perform DFT design rule checking (Spyglass DRC), LEC equivalence checking, and simulation-based DFT validation for assigned partitions. Contribute to scan chain optimization, test data volume (TDV) analysis, and compression ratio tuning under guidance of senior engineers. Support post-silicon bring-up and ATE debug activities for scan, MBIST, and JTAG/IJTAG on hardware. Execute DFT flows within the M1DPx Tessent-based infrastructure; follow established DFT methodology and raise issues proactively. Collaborate with Physical Design and timing teams on DFT implementation constraints. Develop DFT scripts and contribute to automation improvements under direction of senior team members. Document DFT implementation details, coverage results, and debug findings per team standards. What We're Looking For Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4–7 years of DFT experience. Working knowledge of DFT concepts: scan, MBIST, JTAG/IJTAG, ATPG (SAF/TDF), and basic compression/EDT. Hands-on experience with Siemens Tessent (Modus, Shell) and/or Synopsys TestMax (DFT Compiler, TetraMAX). Experience running DFT flows in an RTL or gate-level environment with Synopsys VCS or Cadence Xcelium for simulation. Basic familiarity with LEC tools (Cadence Conformal or Synopsys Formality) for design equivalence checking. Good problem-solving skills and the ability to debug DFT insertion and ATPG issues with support from senior engineers. Familiarity with Linux environment, Tcl/Perl/Python scripting for DFT automation tasks. Strong communication and teamwork skills; ability to collaborate across global multi-site teams. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-RS1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. 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