Senior Staff Engineer, Design For Test

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact As a Senior Staff Engineer, Design For Test at Marvell, you will be a key DFT execution lead within the Custom Silicon Engineering team. Working on leading-edge ASIC/SoC designs for custom AI, XPU, and high-performance compute markets, you will own DFT implementation for complex IP and SoC partitions while contributing to methodology development and mentoring junior engineers. This role requires a specialized DFT engineer recognized as an expert within the team with broad execution and some architectural experience. What You Can Expect Lead DFT implementation for assigned SoC partitions or IP blocks across Custom and XPU programs: scan insertion, MBIST, IJTAG, ATPG pattern generation, and DFT validation using Tessent or TestMax. Execute DFT flows from RTL through gate-level, including Spyglass DRC, LEC equivalence checking, STA for DFT test modes, and test data volume (TDV) optimization. Contribute to DFT architecture discussions for assigned designs; implement defined DFT architectures with high-quality, first-time-right execution. Develop and maintain DFT scripts, automation, and methodology improvements within the M1DPx flow infrastructure. Support post-silicon bring-up: debug scan chains, ATPG pattern failures, MBIST issues, and IJTAG network commissioning on ATE and bench. Collaborate with Physical Design teams on scan chain assignment, OCC insertion, and DFT physical integration. Mentor Staff and junior DFT engineers on methodology and execution best practices. Participate in customer DFT reviews, providing technical support for custom ASIC design engagements. Drive DFT deliverables on schedule: coverage closure, MPR sign-off, and test program handoff to product engineering.

What We're Looking For

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 8+ years of DFT experience. Solid hands-on DFT execution experience: scan insertion, MBIST, JTAG/IJTAG, ATPG (SAF/TDF), EDT compression, and DFT validation (Spyglass DRC, simulation). Proficiency with Siemens Tessent and/or Synopsys TestMax for DFT insertion and ATPG. Experience executing DFT in an RTL-based insertion flow (e.g., Tessent RTL flow) and/or gate-level DFT flow. Working knowledge of LEC, STA for test modes, scan chain optimization, and TDV management. Experience with post-silicon bring-up and ATE debug is a strong plus. Good communication skills; ability to work effectively in a multi-site, geographically distributed team. Track record of delivering DFT on schedule for complex SoC designs at 7nm or below is a plus.

Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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