PD - IP Lead – Sr Staff, Physical Design

Define and execute IP block and partition physical design strategy across projects, aligning schedules, resources, and milestones to company tapeout goals.

Lead mixed signal placement and routing, enforcing analog keepouts, shielding, and DRC aware methodologies while integrating digital logic cleanly.

Own system and block integration for floorplanning, power, placement, CTS, and constraints, ensuring consistent interfaces across hierarchy and reuse

Drive end to end IP physical implementation from RTL handoff through GDSII, managing iterations, ECOs, and closure plans across corners

Develop and maintain block specific flow customizations for synthesis, PNR, EM IR, STA, and physical verification to improve QoR and predictability

Deliver robust constraints methodology, pushing timing intent from system to block and back, maintaining mode and corner correctness for signoff

Run and close subsystem signoff including STA, EM IR, SI, DRC, LVS, antenna, and metal fill, meeting reliability and manufacturability requirements

Optimize clock architecture and CTS for skew, latency, and power, including skew group definitions and balancing across library corners

Collaborate with front end, DFT, packaging, and manufacturing to resolve integration risks, test mode impacts, and physical interface requirements

Provide clear status, risk, and mitigation reporting to leadership, using metrics driven dashboards for PPA, convergence, and schedule predictability