DV - Digital Verification Engineer (Senior levels - Staff +)

Develop and execute verification plans for connectivity IPs and Chiplets

Create and maintain SystemVerilog/UVM-based verification environments

Write and debug SystemVerilog/UVM compliant test cases for block and chip level

Maintain a regression environment for enabling design CI/CD pipelines

Collaborate with design engineers to ensure design quality with continuous microarchitecture, test-plan, and coverage reviews

Develop, maintain, and track various test plan items and progress towards RTL freeze

Stay up to date with industry trends, emerging technologies and progress in standards’ bodies

Ensure IP compliance with Ethernet standards (IEEE 802.3)

Integration 3rd party VIPs and coordinate feature/bug tracking requests

Perform in the capacity of a technical leader for junior verification engineers

Create, improve, maintain DPI based FW simulation environments

Create, improve, maintain GLS environments for functional and power simulations