Digital - Staff Digital Design Engineer - PHY

Architecture & RTL Design

Own D2D PHY digital design from microarchitecture definition through synthesis and PD handoff

Design data path and clocking architecture for UCIe-compliant advanced package PHY

Write RTL for link training, calibration engines, rate adaptation, CDC, FIFO alignment, and lane deskew

Create microarchitecture specs with power analysis, latency metrics, and performance characterization

Make architectural trade-offs balancing performance, power, area, and timing

Synthesis & Optimization

Drive synthesis optimization: area, timing, power, QoR

Create comprehensive SDC constraints for multi-clock domains, false paths, multi-cycle paths, CDC

Generate UPF power specifications with voltage domains, isolation, and retention

Establish LINT/CDC flows with rulesets and waiver management

Deliver synthesis-ready netlists with handoff documentation for physical design

Technical Leadership & Collaboration

Coordinate with analog PHY team on digital control for TX/RX, PLL, calibration

Partner with verification team on testbench requirements, coverage goals, and protocol compliance

Collaborate with physical design on placement guidelines, clock tree requirements, routing constraints

Work with firmware team on register interfaces, link training sequences, runtime control

Mentor 2-3 digital designers on frontend design and synthesis optimization

Drive design reviews and technical decisions across teams