Digital - SerDes Digital Design Lead

Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling, including DSP-based equalization (FFE, DFE, CTLE digital controls), CDR loop logic, and adaptation engines

Design and optimize PHY-level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear-boxing/rate-matching logic

Architect and implement forward error correction (FEC) encoder/decoder blocks including RS-FEC (KP4/KP8), interleaving, and low-latency FEC architectures optimized for 224G/448G link budgets

Drive RTL design quality through lint, CDC/RDC analysis, synthesis optimization, and close collaboration with physical design and timing closure teams on advanced FinFET/GAA process nodes

Collaborate closely with analog/mixed-signal designers on SerDes AFE integration, digital-to-analog interface specification, calibration sequencing, and AMS co-simulation bring-up

Own design deliverables and milestones from RTL development through tapeout signoff; coordinate with verification, DFT, and backend teams to meet aggressive schedules

Define and implement auto-negotiation, link training, and PHY initialization state machines compliant with IEEE 802.3

Develop power-efficient digital architectures with emphasis on clock gating, voltage scaling, and low-power design techniques for data center and AI/ML interconnect applications

Participate in standards bodies and stay current with emerging 224G/448G specifications, OIF CEI, and next-generation interconnect standards

Design firmware-accessible register interfaces, configuration/calibration logic, and DPI-based firmware co-simulation hooks for PHY bring-up and debug

Support post-silicon characterization and debug activities; correlate silicon measurements with pre-silicon simulation results to drive design improvements