Digital - Digital Design Engineer (title will reflect experience)

Bachelors or Masters or Ph.D in Electrical Engineering and related fields, or equivalent

5+ years of experience in high-speed digital design (preferably in retimer, gearbox, Ethernet PMA/PCS logic)

Strong expertise in RTL and Assertion coding with SystemVerilog

Proficiency in taking RTL through synthesis and produce a PPA optimized frontend netlist

Knowledge of Ethernet 802.3 standards’ clauses related to 100G/200G/400G/800G, Auto-Negotiation and Link Training

Strong bias for innovations across all aspects of digital design including automation of mundane activities and methods for quality improvement

Experience integrating 3rd party mixed signal IPs

Proven track record of being part of a start-up like environment

Knowledge of DRAM Controllers/PHYs and HBM Memory a plus