DFT - Staff DFT Engineer

Work with the DFT and Chip Architects to define DFT strategy, methodologies, and implementation plan for various projects (chip_level and stand-alone IP blocks such as PHYs and chiplets)

Implement DFT features in RTL for digital and analog blocks to the defined architecture & plan

Generate patterns (e.g., 1687 PLDs, 1149.x, MBIST, etc.) and validate the same at the RTL & gate level

Generate ATPG patterns (SA/TDF/etc.) and validate the same in 0-delay and SDF-delay based simulations.

Collaborate with Analog/Mixed Signal (AMS) teams to ensure DFT coverage for high-speed interfaces & implement structural tests for digital logic in the analog blocks

Work with circuit architects on advanced testing techniques such as PRBS-based PHY loopback capabilities, internal measurement of high-speed clock networks, etc.

Support flow automation and scripting

Support device bring up in the lab and pattern handoff to operations for high volume manufacturing and qualification (e.g., running patterns in the lab via the TAP controller, post-silicon bring up of patterns on the ATE, pattern bring up for HTOL and other QUAL activities, RMA analysis, etc.)

Document overall test coverage and mitigation strategy to narrow down holes