Senior Static Timing Analysis (STA) Methodology Engineer

• Lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes

• Develop and enhance STA methodologies across the full RTL-to-GDS flow, including early timing estimation, feasibility checks, synthesis and place-and-route optimization, signoff criteria, and post-route ECO strategies

• Architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA and runtime efficiency

• Drive signoff correlation and closure using PrimeTime and related tools (PT-SI, PTPX, PT-ECO)

• Debug timing constraints, resolve timing correlation issues, and develop effective timing closure strategies

• Explore and deploy data-driven and ML-assisted techniques to improve STA automation, predict and prioritize timing risk, and guide optimization across blocks and full-chip

• Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity

• Continuously refine workflows and introduce new technologies to ensure robust, PPA-optimized timing solutions across all product lines

• Provide timing closure guidance and mentorship to design and physical design engineers