Manager, Static Timing Analysis (STA)

Job Details: Job Description: Altera is seeking a Manager, Static Timing Analysis (STA) to lead a team responsible for timing closure and signoff of advanced FPGA designs! This role will play a critical part in ensuring high-performance, power-efficient silicon by driving timing methodology, analysis, and optimization across complex designs. The ideal candidate brings deep STA expertise, strong leadership experience, and a proven ability to collaborate across design, physical implementation, and architecture teams. Key Responsibilities Team Leadership: Build, manage, and mentor a high-performing STA team; drive technical excellence and career development. Timing Closure & Signoff: Own end-to-end STA for FPGA designs, including constraint development, timing analysis, and timing signoff. Methodology Development: Define and implement robust STA methodologies, flows, and best practices to improve timing convergence and design quality. Cross-Functional Collaboration: Partner with RTL design, synthesis, physical design (P&R), and architecture teams to identify and resolve timing issues. Performance Optimization: Drive improvements in performance, power, and area (PPA) through timing-driven design and optimization techniques. Tool & Flow Expertise: Leverage industry-standard EDA tools to analyze timing, debug violations, and automate flows where applicable. Project Execution: Ensure on-time delivery of timing closure milestones across multiple programs. Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success. Estimated Salary Range: $144.6K – $209.3K CAD We use artificial intelligence to screen, assess, or select applicants for the position. This posting is for an existing vacancy. Canadian work experience is not required for this role. Applicants must be eligible for any required Canada export authorizations. Qualifications: Required Qualifications Experience: 10+ years of experience in Static Timing Analysis (STA) for ASIC or FPGA designs. Leadership: 3+ years of experience managing or leading engineering teams. Technical Expertise: Deep knowledge of STA concepts (setup/hold, clock domain crossing, timing constraints) Strong experience with timing signoff tools (e.g., PrimeTime or equivalent) Understanding of synthesis, place & route, and full chip implementation flows Design Flow Knowledge: Solid understanding of: RTL design (Verilog/SystemVerilog) Timing closure methodologies Low-power and high-performance design challenges Debug & Analysis: Strong skills in root-cause analysis of timing violations and driving closure across complex designs. Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. Preferred Qualifications Experience with FPGA architecture and design flows Familiarity with advanced nodes and high-speed designs Exposure to scripting/automation (e.g., Tcl, Python) for timing analysis Experience working in large-scale, distributed engineering environments Why Join Altera Lead critical STA efforts for next-generation FPGA platforms Work on cutting-edge technology in AI, data center, and networking applications Collaborate with world-class engineering teams across silicon design and implementation Job Type: Regular Shift: Shift 1 (Canada) Primary Location: Toronto, Ontario, Canada Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. About Altera Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click "Get Started" below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.